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SPT1175
8-BIT, 20 MSPS CMOS A/D CONVERTER
FEATURES
* * * * * * * 20 MSPS Maximum Conversion Rate Internal Sample-and-Hold Function 90 mW Power Dissipation Internal Voltage Reference Single +5.0 V Power Supply Three-State TTL-Outputs CMOS Compatible Clock
APPLICATIONS
* * * * * * Video Digitizing Image Scanners Personal Computer Video Medical Ultrasound Multimedia Digital Television
GENERAL DESCRIPTION
The SPT1175 is a CMOS two-step A/D converter capable of digitizing full scale analog input signals into 8-bit digital words at a sample rate of 20 MSPS. For most applications, no external sample-and-hold or video driving amplifiers are required due to the device's narrow aperture time, wide bandwidth, and low input capacitance. The SPT1175 operates from a single +5.0 V power supply and has an internal voltage reference which eliminates the need for external reference circuitry. All digital inputs are CMOS compatible and the tri-state outputs are TTL-compatible. The SPT1175 is ideal for most video and image processing applications that require low power dissipation and low cost. The SPT1175 is available in 24-lead plastic SOIC, plastic DIP, and PLCC packages over the commercial temperature range (0 to +70 C). It is also available in die form.
BLOCK DIAGRAM
VRB VRBS DVDD DGND OE Coarse Sampling Amplifier
Latch
Encoder DO (LSB) D1 Error Correction Circuit Data Latches and 3-State Output Buffer D2 D3 D4 D5 D6
VIN
Reference Matrix
Fine Sampling Amplifier Fine Sampling Amplifier
D7 (MSB) Encoder Analog Mux Latch
Timing Generator
CLK
VRT
VRTS
AGND AVD
DVDD
AGND
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)(1) 25 C
Supply Voltages VDD ........................................................... -0.5 to +7.0 V Input Voltages Analog Input .............................................. AGND to VDD Reference Input Voltage ........................... AGND to VDD ESD Susceptibility(2) ................................................. 1,500 V Temperature Operating Temperature ................................. 0 to +70 C Junction Temperature ........................................... 175 C Lead Temperature, (soldering 10 seconds) .......... 300 C Storage Temperature ................................ -55 to +125 C
Notes: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications. 2. 100 pF discharged through a 1.5 k resistor (human body model).
ELECTRICAL SPECIFICATIONS
TA= +25 C, AVDD=DVDD=+5.0 V, AGND=DGND=0.0 V, VRB=+0.6 V and VRT=+2.6 V, unless otherwise specified.
PARAMETERS Resolution DC Accuracy (+25 C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth Reference Input Reference Ladder Resistance Reference Current Reference Input Voltage Internal Bias
TEST CONDITIONS
TEST LEVEL
MIN 8
SPT1175 TYP
MAX
UNITS Bits
I I I I I VI V V I I IV IV I I VRB 100 12 200 5.0 0 0.55 1.9
0.8 0.6 Guaranteed
1.2 1.0
LSB LSB
VRT 5.0 200 15
V A k pF MHz mA V V V V
VRB VRT VRB VRT-VRB Short VRT and VRTS Short VRB and VRBS
300 6.7 0.6 2.6 0.60 2.0
400 10.0 2.8 0.65 2.1
Offset Voltage Error Top Bottom Timing Characteristics Maximum Conversion Rate Output Data Delay (td) Output Data Delay (Tdish, Tdisl) Data Valid Time (Teneh, Tenel) Sampling Time Offset 1 MHz Input Sine Wave (High Z) Tri-State Circuit
I I I IV IV IV IV
-18 0 20
-25 10 30 18
-68 40
mV mV MSPS ns ns ns ns
30 100 100
5
10
NOTE: It is strongly recommended that all of the supply pins (AVDD, DVDD) be powered from the same source.
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ELECTRICAL SPECIFICATIONS
TA=+25 C, AVDD=DVDD=+5.0 V, AGND=DGND=0.0 V, VRB=+0.6 V and VRT=+2.6 V, unless otherwise specified. PARAMETERS Dynamic Performance Signal-To-Noise Ratio fIN=1.0 MHz fIN=3.58 MHz fIN=10 MHz Spurious Free Dynamic Range fIN=1.0 MHz fIN=3.58 MHz fIN=10 MHz Differential Phase Differential Gain Digital Inputs Input Current, Logic High Input Current, Logic Low Pulse Width High (CLK) Pulse Width Low (CLK) Voltage, Logic High Voltage, Logic Low Digital Outputs Output Current, High Output Current, Low Output Current, High Z Voltage High Voltage Low Power Supply Requirements Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Supply Voltage Difference Supply Current Power Dissipation TEST CONDITIONS fS= 20 MSPS I I V fS= 20 MSPS I I V V V I I IV IV I I IV IV IV I I IV IV IV I I 44 41 47 44 33 0.7 1.0 1.0 1.0 15 15 4.0 1.0 -1.1 3.5 16 4.0 0.4 +4.75 +4.75 -0.1 +5.0 +5.0 0.0 18 90 +5.25 +5.25 0.1 27 135 dB dB dB Degrees % A A ns ns V V mA mA A V V V V V mA mW 44 43 46 45 39 dB dB dB TEST LEVEL MIN SPT1175 TYP MAX UNITS
NTSC 20 IRE Mod Ramp fS = 14.3 MSPS VDD = 5.25 V, VIH = VDD VDD = 5.25 V, VIL = DGND
VDD = 4.75 V VDD = 4.75 V VDD = 5.25 V, OE= VDD
(AVDD -DVDD) fS=20 MSPS
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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Table I - Output Coding INDEX 0 1 2 .... 123 124 125 .... 254 255 ANALOG INPUT (V) 0.6078125 0.6078125 ~ 0.6156260 0.6156250 ~ 0.6234375 .... 1.5921875 ~ 1.6000000 1.6000000 ~ 1.6078125 1.6078125 ~ 1.6156250 .... 2.5843750 ~2.5921875 2.5921875 ~ DIGITAL OUTPUT 00000000 00000001 00000010 .... 01111111 10000000 10000001 .... 11111110 11111111 VRB=0.6 V VRT=2.6 V 1 LSB=7.8125 mV
Figure 1A: Timing Diagram
VIN (n) VIN (n+1) VIN (n+2) VIN (n+3)
VIN Clock Data Data (n-3) Data (n-2) Data (n-1) Data (n)
td
Figure 1B: Tri-State Output Timing Diagram
50% OE 2.5 V 220 DUT 50 pF 50% OE VOH VOL
2.5 V 90%
OE
50% 90%
2.5 V 10% TdisL VOL TeneL
OE
50% 90% VOH
10% 2.5 V TdisH 2.5 V
TeneH
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TYPICAL INTERFACE CIRCUIT
The SPT1175 is an 8-bit analog-to-digital converter which uses a two-step, ping-pong architecture to perform conversions up to 20 MSPS. Figure 2 shows the typical interface requirements when using the SPT1175 in normal operation. The following sections describe the function and operation of the device. POWER SUPPLIES AND GROUNDING The SPT1175 operates from a single +5 V power supply. AVDD and DVDD must be supplied from the same source (analog +5 V) to prevent a latch-up condition due to power supply sequencing. Each power supply pin should be bypassed as closely as possible to the device. For optimal performance, both the AGND and DGND should be connected to the system's analog ground plane. ANALOG INPUT AND VOLTAGE REFERENCE The SPT1175 input voltage range is VRT>VIN>VRB. Two reference voltages (VRT and VRB) are required for device operation. These voltages may be generated externally or the SPT1175's internal reference may be used. Inside the SPT1175, reference resistors are placed between AVDD and VRTS and between AGND and VRBS so that VRTS and VRBS generate the 2.6 V and 0.6 V references respectively. (See figure 3.) In order to utilize the internal self-bias reference voltage, VRTS is to be shorted with VRT and the Figure 2 - Typical Interface Circuit
10 10 10 + 10 + + +5 R1 2k Q1 FB +5 V GND -5 +5 +15 -15 + GND +15 -5 -15 +5
VRBS pin is to be shorted to the VRB pin. The self-bias internal reference is not as stable over temperature and supply variations as externally generated reference voltages but will perform well in many commercial video applications. Figure 3 - Reference Circuit Diagram
SPT1175
AVDD 5.0V AGND 0V
DIGITAL INPUTS AND OUTPUTS The analog input is sampled and tracked on the first 'H' cycle of the external clock and is held from the falling edge of CLK. The output remains valid (output hold time), and the new data becomes valid (output delay time) after the rising edge of CLK, delayed by 2.5 clock cycles. The clock input and output enable input must be driven at CMOS-compatible levels. EVALUATION BOARD The EB1175 evaluation board is available to aid designers in demonstrating the full performance of the SPT1175. This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction DAC. An application note describing the operation of the board is available. Contact the factory for price and delivery.
VRTS
2.6 V
VRB VRT
0.6 V
VRBS
13 14 15
DVDD AVDD AVDD VRTS VRT AVDD VIN AGND AGND VRBS VRB DGND
CLK 12 DVDD 11 D7 10(MSB) D6 9 D5 8 D4 7 D3 6 D2 5 D1 4 D0 DGND 3 (LSB) 2 Outputs
750
R9 C28
-15 +15
16
+ 4 7 +5 V D1 R37
C29
VIN
U1=Eleantec, EL2030 U2=OP.07 D1=D2=RCA, SK9091 Q1=Q2=2N2222A FR=FairRite, 2743001111 All capacitors are 0.01 F unless otherwise specified.
17 18 19
D2
3 75 R35 2_
U1
750 R36
750
20 21
_ 10 k R6 C58 R10 2 U2 3+ C59
6 R15 10 C8 C61
22 23 24
R8 -5 750 +5 R2 R13 Q2 2k 200
7.5 k -15
C60 -15 +15
OE 1
3-ST EN +5
NOTE: AVDD and DVDD must be supplied from the same source (Analog +5 V) to prevent a latch-up condition due to power supply sequencing.
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PACKAGE OUTLINES
24-Lead Plastic DIP
INCHES MAX 0.230 0.200 0.023 0.070 0.015 0.195 0.310 1.285 MILLIMETERS MIN MAX 3.30 2.92 0.36 1.14 2.54 0.20 2.92 7.62 6.10 29.97 0.13 5.84 5.08 0.58 1.78 0.00 0.38 4.95 0.00 7.87 32.64
K
SYMBOL A B C D
MIN
0.130 0.115 0.014 0.045 .100 typ 0.008 0.115 .30 typ 0.240 1.180 .005 typ
24
I
1
E F G H I J K
J H A G
B
F D
C
E
24-Lead SOIC
INCHES SYMBOL
24
MILLIMETERS MAX 0.606 MIN 14.90 1.27 typ 0.022 0.012 0.089 0.028 0.327 0.220 0.35 0.15 1.70 0.30 7.50 5.20 0.55 0.30 2.25 0.70 8.30 5.60 MAX 15.40
MIN 0.587 .050 typ 0.014 0.006 0.067 0.012 0.295 0.205
A B
IH
C D E
1
F G H I
A F B C D E G
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PACKAGE OUTLINES
28-Lead PLCC
INCHES SYMBOL A B C D E F G H I
C
MILLIMETERS MIN 11.43 12.32 45 4.19 .56 typ 4.57 typ 1.27 typ 0.99 MAX 11.58 12.57 4.45 0.25 0.00 0.00 0.00 10.92 0.456 0.495 0.175 0.010
MIN 0.450 0.485 45 0.165 0.022 typ 0.18 typ 0.05 typ 0.039
MAX
0.430
Pin 1
H
Pin 1
TOP VIEW
G I F
BOTTOM VIEW
A B D
E
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PIN ASSIGNMENTS
OE DGND DO (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DVDD CLK DGND VRB VRBS AGND AGND
PIN FUNCTIONS
Name
OE
DIP and SOIC
VIN AVDD VRT VRTS AVDD AVDD DVDD
DGND D0 D1-6 D7 DVDD CLK AVDD VRTS VRT VIN AGND VRBS VRB
Function Tri-State Output Enable Tri-State When OE = DVDD, Enable When OE = DGND Digital Ground Digital Output Data (LSB) Digital Output Data Digital Output Data (MSB) Digital Supply CMOS Digital Clock Input Analog Supply Internal Self-Biased Reference Top Shorted with VRT (pin 17). Generates 2.6 V. Reference Resistor Top Side Analog Input Analog Ground Internal Self-Biased Reference Bottom Shorted with VRB (pin 23). Generates 0.6 V. Reference Resistor Bottom Side
DGND 28
DO 4
OE 2
VRBS 26
DGND 3
N/C 1
VRB 27
D1 D2 D3 N/C D4
5 6 7 8 9
25 22 23
AGND AGND VIN N/C AVDD VRT VRTS
PLCC
22 21 20 19
D5 10 D6 11
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE SPT1175ACN 0 to +70 C SPT1175ACP 0 to +70 C SPT1175ACS 0 to +70 C SPT1175ACU +25 C *See the die specification for guaranteed electrical performance. PACKAGE TYPE 24L Plastic Dip 28L PLCC 24L SOIC Die*
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
12 D7
14 CLK
16 DVDD
18 AVDD
13 DVDD
15 N/C
17 AVDD
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